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rev.0.10 jul 20, 2007 page 1 of 65 rej03b0217-0010 r8c/2h group, r8c/2j group renesas mcu 1. overview 1.1 features the r8c/2h group and r8c/2j group of single-chip mcus incorporate the r8c/tiny series cpu core, employing sophisticated instructions for a high level of efficiency. with 1 mbyte of address space and is capable of executing instructions at high speed. in addition, the cpu core boasts a multiplier for high-speed operation processing. power consumption is low, and the supported operating modes allow additional power control. these mcus also use an anti-noise configuration to reduce emissions of electro magnetic noise and are designed to withstand emi. integration of many peripheral functions, including multifun ction timer and serial inte rface, reduces the number of system components. 1.1.1 applications electric power meters, electronic household applianc es, office equipment, audio equipment, consumer equipment, etc. rej03b0217-0010 rev.0.10 jul 20, 2007 preliminary notice: this is not a final specification. some parametric limits are subject to change.
r8c/2h group, r8c/2j group 1. overview rev.0.10 jul 20, 2007 page 2 of 65 rej03b0217-0010 under development preliminary specification specications in this manual ar e tentative and subject to change 1.1.2 specifications table 1.1 outlines the specifications for r8c/2h group and table 1.2 out lines the specifications for r8c/2j group. note: 1. specify the d version if d ve rsion functions are to be used. table 1.1 specifications for r8c/2h group item function specification cpu central processing unit r8c/tiny series core ? number of fundamental instructions: 89 ? minimum instruction execution time: 125 ns (f(xin) = 8 mhz, vcc = 2.7 to 5.5 v) 250 ns (f(xin) = 4 mhz, vcc = 2.2 to 5.5 v) ? multiplier: 16 bits 16 bits 32 bits ? multiply-accumulate instruction: 16 bits 16 bits + 32 bits 32 bits ? operation mode: single-chip mode (address space: 1 mbyte) memory rom, ram refer to table 1.3 product list for r8c/2h group . power supply voltage detection voltage detection circuit ? power-on reset ? voltage detection 3 comparator ? 2 circuits (shared with voltage monitor 1 and voltage monitor 2) ? external reference voltage input is available i/o ports cmos i/o ports: 16, selectable pull-up resistor clock clock generation circuits ? 2 circuits: on-chip oscillator (high-speed, low-speed) (high-speed on-chip oscillator has a frequency adjustment function), xcin clock oscillati on circuit (32 khz) ? frequency divider circuit: dividing selectable 1, 2, 4, 8, and 16 ? low power consumption modes: standard operating mode (low-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillato r), wait mode, stop mode real-time clock (timer re) interrupts ? external: 3 sources, inte rnal: 17 sources, software: 4 sources ? priority levels: 7 levels watchdog timer 15 bits 1 (with prescaler), reset start selectable timer timer ra 8 bits 1 (with 8-bit prescaler) timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse wi dth measurement mode, pulse period measurement mode timer rb 8 bits 1 (with 8-bit prescaler) timer mode (period timer), programmable waveform generation mode (pwm output), programmable one-shot generation mode, programmable wait one- shot generation mode timer re 8 bits 1 real-time clock mode (count seconds, minu tes, hours, days of week), output compare mode timer rf 16 bits 1 (with capture/compare register pin and compare register pin) input capture mode, output compare mode serial interface uart0, uart2 clock synchronous serial i/o/uart 2 lin module hardware lin: 1 (timer ra, uart0) flash memory ? programming and erasur e voltage: vcc = 2.7 to 5.5 v ? programming and erasure endurance: 100 times ? program security: rom code protect, id code check ? debug functions: on-chip debug, on-board flash rewrite function operating frequency/supply voltage f(xin) = 8 mhz (vcc = 2.7 to 5.5 v) f(xin) = 4 mhz (vcc = 2.2 to 5.5 v) current consumption tbd operating ambient temperature -20 to 85 c (n version) -40 to 85 c (d version) (1) package 20-pin lssop package code: plsp0020jb-a (previous code: 20p2f-a)
r8c/2h group, r8c/2j group 1. overview rev.0.10 jul 20, 2007 page 3 of 65 rej03b0217-0010 under development preliminary specification specications in this manual ar e tentative and subject to change note: 1. specify the d version if d ve rsion functions are to be used. table 1.2 specifications for r8c/2j group item function specification cpu central processing unit r8c/tiny series core ? number of fundamental instructions: 89 ? minimum instruction execution time: 125 ns (f(xin) = 8 mhz, vcc = 2.7 to 5.5 v) 250 ns (f(xin) = 4 mhz, vcc = 2.2 to 5.5 v) ? multiplier: 16 bits 16 bits 32 bits ? multiply-accumulate instruction: 16 bits 16 bits + 32 bits 32 bits ? operation mode: single-chip mode (address space: 1 mbyte) memory rom, ram refer to table 1.4 product list for r8c/2j group . power supply voltage detection voltage detection circuit ? power-on reset ? voltage detection 3 comparator ? 2 circuits (shared with voltage monitor 1 and voltage monitor 2) ? external reference voltage input is available i/o ports cmos i/o ports: 12, selectable pull-up resistor clock clock generation circuits ? 1 circuits: on-chip oscillator (high-speed, low-speed) (high-speed on-chip oscillator has a frequency adjustment function), ? frequency divider circuit: dividing selectable 1, 2, 4, 8, and 16 ? low power consumption modes: standard operating mode (high-speed on-ch ip oscillator, low-speed on-chip oscillator), wait mode, stop mode interrupts ? external: 3 sources, inte rnal: 14 sources, software: 4 sources ? priority levels: 7 levels watchdog timer 15 bits 1 (with prescaler), reset start selectable timer timer ra 8 bits 1 (with 8-bit prescaler) timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse wi dth measurement mode, pulse period measurement mode timer rb 8 bits 1 (with 8-bit prescaler) timer mode (period timer), programmable waveform generation mode (pwm output), programmable one-shot generation mode, programmable wait one- shot generation mode timer rf 16 bits 1 (with capture/compare register pin and compare register pin) input capture mode, output compare mode serial interface uart0 clock synchronous serial i/o/uart 1 lin module hardware lin: 1 (timer ra, uart0) flash memory ? programming and erasur e voltage: vcc = 2.7 to 5.5 v ? programming and erasure endurance: 100 times ? program security: rom code protect, id code check ? debug functions: on-chip debug, on-board flash rewrite function operating frequency/supply voltage f(xin) = 8 mhz (vcc = 2.7 to 5.5 v) f(xin) = 4 mhz (vcc = 2.2 to 5.5 v) current consumption tbd operating ambient temperature -20 to 85 c (n version) -40 to 85 c (d version) (1) package 20-pin lssop package code: plsp0020jb-a (previous code: 20p2f-a)
r8c/2h group, r8c/2j group 1. overview rev.0.10 jul 20, 2007 page 4 of 65 rej03b0217-0010 under development preliminary specification specications in this manual ar e tentative and subject to change 1.2 product list table 1.3 lists product list for r8c/2h group, figure 1.1 shows a part number, memory size, and package of r8c/2h group. table 1.4 lists product list for r8c/2j gr oup, figure 1.2 shows a part number, memory size, and package of r8c/2j group. (d): under development figure 1.1 part number, memory size, and package of r8c/2h group table 1.3 product list for r8c/2h group current of jul. 2007 part no. rom capacity ram capacity package type remarks r5f212h1snsp (d) 4 kbytes 256 bytes plsp0020jb-a n version r5f212h2snsp (d) 8 kbytes 384 bytes plsp0020jb-a r5f212h1sdsp (d) 4 kbytes 256 bytes plsp0020jb-a d version r5f212h2sdsp (d) 8 kbytes 384 bytes plsp0020jb-a part no. r 5 f 21 2h 1 s n sp package type: sp: plsp0020jb-a classification n: operating ambient temperature -20c to 85c d: operating ambient temperature -40c to 85c s: low-voltage version (other no symbols) rom capacity 1: 4 kb 2: 8 kb r8c/2h group r8c/tiny series memory type f: flash memory version renesas mcu renesas semiconductor
r8c/2h group, r8c/2j group 1. overview rev.0.10 jul 20, 2007 page 5 of 65 rej03b0217-0010 under development preliminary specification specications in this manual ar e tentative and subject to change (d): under development figure 1.2 part number, memory size, and package of r8c/2j group table 1.4 product list for r8c/2j group current of jul. 2007 part no. rom capacity ram capacity package type remarks r5f212j0snsp (d) 2 kbytes 256 bytes plsp0020jb-a n version R5F212J1SNSP (d) 4 kbytes 384 bytes plsp0020jb-a r5f212j0sdsp (d) 2 kbytes 256 bytes plsp0020jb-a d version r5f212j1sdsp (d) 4 kbytes 384 bytes plsp0020jb-a part no. r 5 f 21 2j 1 s n sp package type: sp: plsp0020jb-a classification n: operating ambient temperature -20c to 85c d: operating ambient temperature -40c to 85c s: low-voltage version (other no symbols) rom capacity 0: 2 kb 1: 4 kb r8c/2j group r8c/tiny series memory type f: flash memory version renesas mcu renesas semiconductor
r8c/2h group, r8c/2j group 1. overview rev.0.10 jul 20, 2007 page 6 of 65 rej03b0217-0010 under development preliminary specification specications in this manual ar e tentative and subject to change 1.3 block diagram figure 1.3 shows a block diagram of r8c/2h group and figure 1.4 shows a block diagram of r8c/2j group. figure 1.3 block diagram of r8c/2h group r8c/tiny series cpu core memory watchdog timer (15 bits) rom (1) ram (2) multiplier r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports notes: 1. rom size varies with mcu type. 2. ram size varies with mcu type. system clock generation circuit high-speed on-chip oscillator low-speed on-chip oscillator xcin-xcout timers timer ra (8 bits) timer rb (8 bits) timer re (8 bits) timer rf (16 bits) uart or clock synchronous serial i/o (8 bits 2 channels) lin module (1 channel) 8 port p1 2 port p3 3 port p4 3 port p6 peripheral functions voltage detection circuit (3 circuits) comparator (2 circuits)
r8c/2h group, r8c/2j group 1. overview rev.0.10 jul 20, 2007 page 7 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change figure 1.4 block diagram of r8c/2j group r8c/tiny series cpu core memory watchdog timer (15 bits) rom (1) ram (2) multiplier r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports notes: 1. rom size varies with mcu type. 2. ram size varies with mcu type. system clock generation circuit high-speed on-chip oscillator low-speed on-chip oscillator timers timer ra (8 bits) timer rb (8 bits) timer rf (16 bits) uart or clock synchronous serial i/o (8 bits 1 channels) lin module (1 channel) 8 port p1 2 port p3 peripheral functions voltage detection circuit (3 circuits) comparator (2 circuits) 1 port p6 1 port p4
r8c/2h group, r8c/2j group 1. overview rev.0.10 jul 20, 2007 page 8 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change 1.4 pin assignment figure 1.5 shows pin assignment (top view) of r8c/2h group. table 1.5 outlines the pin name information by pin number of r8c/2h group. figure 1.6 shows pin assignment (top view) of r8c/2j group. table 1.6 outlines the pin name information by pin number of r8c/2j group. figure 1.5 pin assignment (top view) of r8c/2h group 1 2 3 4 5 6 7 8 9 10 20 p6_3/txd2 19 p3_3/trfo10/trfi 18 p1_0/ki0/trfo00/vcmp1 17 p1_1/ki1/trfo01/vcmp2 16 p6_5/clk2 15 p1_2/ki2/trfo02/cvref 14 p1_3/ki3/vcout1/trbo 13 p1_4/txd0 12 p1_5/rxd0/(traio)/(int1) (1) 11 p1_6/clk0/vcout2 p6_4/rxd2 p3_7/trao/trfo11 reset p4_4/xcout vss p4_3/xcin vcc mode p4_5/int0 p1_7/traio/int1 r8c/2h group plsp0020jb-a (20p2f-a) (top view) notes: 1. can be assigned to the pin in parentheses by a program. 2. confirm the pin 1 position on the package by referring to the package dimensions.
r8c/2h group, r8c/2j group 1. overview rev.0.10 jul 20, 2007 page 9 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change note: 1. can be assigned to the pin in parentheses by a program. table 1.5 pin name information by pin number of r8c/2h group pin number control pin port i/o pin functions for of peripheral modules interrupt timer serial interface comparator 1 p6_4 rxd2 2 p3_7 trao/trfo11 3 reset 4 xcout p4_4 5vss 6 xcin p4_3 7vcc 8mode 9 p4_5 int0 10 p1_7 int1 traio 11 p1_6 clk0 vcout2 12 p1_5 (int1 ) (1) (traio) (1) rxd0 13 p1_4 txd0 14 p1_3 ki3 trbo vcout1 15 p1_2 ki2 trfo02 cvref 16 p6_5 clk2 17 p1_1 ki1 trfo01 vcmp2 18 p1_0 ki0 trfo00 vcmp1 19 p3_3 trfo10/trfi 20 p6_3 txd2
r8c/2h group, r8c/2j group 1. overview rev.0.10 jul 20, 2007 page 10 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change figure 1.6 pin assignment (top view) of r8c/2j group 1 2 3 4 5 6 7 8 9 10 20 nc 19 p3_3/trfo10/trfi 18 p1_0/ki0/trfo00/vcmp1 17 p1_1/ki1/trfo01/vcmp2 16 p6_5 15 p1_2/ki2/trfo02/cvref 14 p1_3/ki3/vcout1/trbo (1) 13 p1_4/txd0 12 p1_5/rxd0/(traio)/(int1) (1) 11 p1_6/clk0/vcout2 nc p3_7/trao/trfo11 reset nc vss nc vcc mode p4_5/int0 p1_7/traio/int1 r8c/2j group plsp0020jb-a (20p2f-a) (top view) notes: 1. can be assigned to the pin in parentheses by a program. 2. confirm the pin 1 position on the package by referring to the package dimensions. nc?non-connection
r8c/2h group, r8c/2j group 1. overview rev.0.10 jul 20, 2007 page 11 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change note: 1. can be assigned to the pin in parentheses by a program. 2. nc(non-connection) table 1.6 pin name information by pin number of r8c/2j group pin number control pin port i/o pin functions for of peripheral modules interrupt timer serial interface comparator 1 nc (2) 2 p3_7 trao/trfo11 3 reset 4 nc (2) 5vss 6 nc (2) 7vcc 8mode 9 p4_5 int0 10 p1_7 int1 traio 11 p1_6 clk0 vcout2 12 p1_5 (int1 ) (1) (traio) (1) rxd0 13 p1_4 txd0 14 p1_3 ki3 trbo vcout1 15 p1_2 ki2 trfo02 cvref 16 p6_5 17 p1_1 ki1 trfo01 vcmp2 18 p1_0 ki0 trfo00 vcmp1 19 p3_3 trfo10/trfi 20 nc (2)
r8c/2h group, r8c/2j group 1. overview rev.0.10 jul 20, 2007 page 12 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change 1.5 pin functions table 1.7 pin functions of r8c/2h group and table 1.8 pin functions of r8c/2j group. i: input o: output i/o: input and output note: 1. refer to the oscillator manufacturer for oscillation characteristics. table 1.7 pin functions of r8c/2h group type symbol i/o type description power supply input vcc, vss ? apply 2.2 v to 5.5 v to the vcc pin. apply 0 v to the vss pin. reset input reset i input ?l? on this pin resets the mcu. mode mode i connect this pin to vcc via a resistor. xcin clock input xcin i these pins are provided for xcin clock generation circuit i/o. connect a crystal oscillator between the xcin and xcout pins. (1) to use an external clock, input it to the xcin pin and leave the xcout pin open. xcin clock output xcout o int interrupt input int0 , int1 iint interrupt input pins key input interrupt ki0 to ki3 i key input interrupt input pins timer ra traio i/o ti mer ra i/o pin trao o timer ra output pin timer rb trbo o timer rb output pin timer rf trfi i timer rf input pin trfo00 to trfo02, trfo10 to trfo11 o timer rf output pins serial interface clk0, clk2 i/o clock i/o pin rxd0, rxd2 i serial data input pin txd0, txd2 o serial data output pin comparator vcmp1, vcmp2 i analog input pins to comparator cvref i reference voltage input pin to comparator vcout1, vcout2 o comparator output pins i/o port p1_0 to p1_7, p3_3, p3_7, p4_3 to p4_5, p6_3 to p6_5 i/o cmos i/o ports. each port has an i/o select direction register, allowing each pin in the port to be directed for input or output individually. any port set to input can be set to use a pull-up resistor or not by a program.
r8c/2h group, r8c/2j group 1. overview rev.0.10 jul 20, 2007 page 13 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change i: input o: output i/o: input and output table 1.8 pin functions of r8c/2j group type symbol i/o type description power supply input vcc, vss ? apply 2.2 v to 5.5 v to the vcc pin. apply 0 v to the vss pin. reset input reset i input ?l? on this pin resets the mcu. mode mode i connect this pin to vcc via a resistor. int interrupt input int0 , int1 iint interrupt input pins key input interrupt ki0 to ki3 i key input interrupt input pins timer ra traio i/o ti mer ra i/o pin trao o timer ra output pin timer rb trbo o timer rb output pin timer rf trfi i timer rf input pin trfo00 to trfo02, trfo10 to trfo11 o timer rf output pins serial interface clk0 i/o clock i/o pin rxd0 i serial data input pin txd0 o serial data output pin comparator vcmp1, vcmp2 i analog input pins to comparator cvref i reference voltage input pin to comparator vcout1, vcout2 o comparator output pins i/o port p1_0 to p1_7, p3_3, p3_7, p4_5, p6_5 i/o cmos i/o ports. each port has an i/o select direction register, allowing each pin in the port to be directed for input or output individually. any port set to input can be set to use a pull-up resistor or not by a program.
r8c/2h group, r8c/2j group 2. central processing unit (cpu) rev.0.10 jul 20, 2007 page 14 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change 2. central processi ng unit (cpu) figure 2.1 shows the cpu registers. the cpu contains 13 registers. r0, r1, r2, r3, a0, a1, and fb configure a register bank. there are two sets of register bank. figure 2.1 cpu registers r2 b31 b15 b8b7 b0 data registers (1) address registers (1) r3 r0h (high-order of r0) r2 r3 a0 a1 intbh b15 b19 b0 intbl fb frame base register (1) the 4 high order bits of intb are intbh and the 16 low order bits of intb are intbl. interrupt table register b19 b0 usp program counter isp sb user stack pointer interrupt stack pointer static base register pc flg flag register carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved bit processor interrupt priority level reserved bit c ipl d z s b o i u b15 b0 b15 b0 b15 b0 b8 b7 note: 1. these registers comprise a regist er bank. there are two register banks. r1h (high-order of r1) r0l (low-order of r0) r1l (low-order of r1)
r8c/2h group, r8c/2j group 2. central processing unit (cpu) rev.0.10 jul 20, 2007 page 15 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change 2.1 data registers (r 0, r1, r2, and r3) r0 is a 16-bit register for transfer, ar ithmetic, and logic operations. the same applies to r1 to r3. r0 can be split into high-order bits (r0h) and low-order bits (r0l) to be used separately as 8-bit data registers. r1h and r1l are analogous to r0h and r0l. r2 can be combined with r0 and used as a 32-bit data register (r2r0). r3r1 is analogous to r2r0. 2.2 address registers (a0 and a1) a0 is a 16-bit register for address register indirect addr essing and address register relative addressing. it is also used for transfer, arithmetic, and logic operations. a1 is analogous to a0. a1 can be combined with a0 to be used as a 32-bit address register (a1a0). 2.3 frame base register (fb) fb is a 16-bit register for fb relative addressing. 2.4 interrupt table register (intb) intb is a 20-bit register th at indicates the start address of an interrupt vector table. 2.5 program counter (pc) pc is 20 bits wide and indicates the addres s of the next instruction to be executed. 2.6 user stack pointer (usp) a nd interrupt stack pointer (isp) the stack pointers (sp), usp, and isp, are each 16 bits wide. the u flag of flg is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register for sb relative addressing. 2.8 flag register (flg) flg is an 11-bit register indicating the cpu state. 2.8.1 carry flag (c) the c flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 debug flag (d) the d flag is for debugging only. set it to 0. 2.8.3 zero flag (z) the z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 sign flag (s) the s flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 register bank select flag (b) register bank 0 is selected when the b flag is 0. regi ster bank 1 is selected when this flag is set to 1. 2.8.6 overflow flag (o) the o flag is set to 1 when an operation results in an overflow; otherwise to 0.
r8c/2h group, r8c/2j group 2. central processing unit (cpu) rev.0.10 jul 20, 2007 page 16 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change 2.8.7 interrupt enable flag (i) the i flag enables maskable interrupts. interrupt are disabled when the i flag is set to 0, and are enabled when the i flag is set to 1. the i flag is set to 0 when an interrupt request is acknowledged. 2.8.8 stack pointer select flag (u) isp is selected when the u flag is set to 0; usp is selected when the u flag is set to 1. the u flag is set to 0 when a hardware interrupt requ est is acknowledged or the int instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide and assigns processor interrupt priority le vels from level 0 to level 7. if a requested interrupt has higher priori ty than ipl, the interrupt is enabled. 2.8.10 reserved bit if necessary, set to 0. when read, the content is undefined.
r8c/2h group, r8c/2j group 3. memory rev.0.10 jul 20, 2007 page 17 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change 3. memory figure 3.1 is a memory map of r8c/2h group and figure 3. 2 is a memory map of r8c/2j group. the r8c/2h group has 1 mbyte of address space from addresses 00000h to fffffh. the internal rom is allocated lower addresses, beginning with address 0 ffffh. for example, a 4-kbyte internal rom area is allocated addr esses 0f000h to 0ffffh. the fixed interrupt vector table is al located addresses 0ffdch to 0ffffh. they store th e starting address of each interrupt routine. the internal ram is allocated higher addresses beginni ng with address 00400h. for example, a 256-bytes internal ram area is allocated addresses 00400h to 004ffh. the internal ram is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. special function registers (sfrs) are allocated addresses 00000h to 002ffh. the peripheral function control registers are allocated here. all addresses within the sfr, which have nothing allocated are reserved for fu ture use and cannot be accessed by users. figure 3.1 memory map of r8c/2h group undefined instruction overflow brk instruction address match single step watchdog timer/voltage monitor/comparator (reserved) (reserved) reset 00400h 002ffh 00000h internal ram sfr (refer to 4. special function registers (sfrs) ) 0ffffh 0ffdch note: 1. the blank regions are reserved. do not access locations in these regions. fffffh 0ffffh 0yyyyh internal rom (program rom) expanded area 0xxxh part number internal rom internal ram size size r5f212h1snsp, r5f212h1sdsp r5f212h2snsp, r5f212h2sdsp 4 kbytes 8 kbytes 0f000h 0e000h 256 bytes 384 bytes 004ffh 0057fh address 0yyyyh address 0xxxxh
r8c/2h group, r8c/2j group 3. memory rev.0.10 jul 20, 2007 page 18 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change figure 3.2 memory map of r8c/2j group undefined instruction overflow brk instruction address match single step watchdog timer/voltage monitor/comparator (reserved) (reserved) reset 00400h 002ffh 00000h internal ram sfr (refer to 4. special function registers (sfrs) ) 0ffffh 0ffdch note: 1. the blank regions are reserved. do not access locations in these regions. fffffh 0ffffh 0yyyyh internal rom (program rom) expanded area 0xxxh part number internal rom internal ram size size r5f212j0snsp, r5f212j0sdsp R5F212J1SNSP, r5f212j1sdsp 2 kbytes 4 kbytes 0f800h 0f000h 256 bytes 384 bytes 004ffh 0057fh address 0yyyyh address 0xxxxh
r8c/2h group, r8c/2j group 4. special function registers (sfrs) rev.0.10 jul 20, 2007 page 19 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change 4. special function registers (sfrs) an sfr (special function register) is a control register for a peripheral function. tables 4.1 to 4.12 list the special function registers. table 4.1 sfr information (1) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. the csproini bit in the ofs register is set to 0. 3. this register is not implemented in the r8c/2j group. address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 00h 0005h processor mode register 1 pm1 00h 0006h system clock control register 0 cm0 01001000b 0007h system clock control register 1 cm1 00h 0008h 0009h 000ah protect register prcr 00h 000bh 000ch system clock select register (3) ocd 00000100b 000dh watchdog timer reset register wdtr xxh 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdc 00x11111b 0010h address match interrupt register 0 rmad0 00h 0011h 00h 0012h 00h 0013h address match interrupt enable register aier 00h 0014h address match interrupt register 1 rmad1 00h 0015h 00h 0016h 00h 0017h 0018h 0019h 001ah 001bh 001ch count source protection mode register cspr 00h 10000000b (2) 001dh 001eh 001fh 0020h high-speed on-chip oscillator control register 0 hra0 00h 0021h high-speed on-chip oscillator control register 1 hra1 when shipping 0022h high-speed on-chip oscillator control register 2 hra2 00h 0023h 0024h 0025h 0026h 0027h 0028h clock prescale r reset flag (3) cpsrf 00h 0029h high-speed on-chip oscillator control register 4 fra4 when shipping 002ah 002bh high-speed on-chip oscillator control register 6 fra6 when shipping 002ch 002dh 002eh 002fh
r8c/2h group, r8c/2j group 4. special function registers (sfrs) rev.0.10 jul 20, 2007 page 20 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change table 4.2 sfr information (2) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register. 3. the lvd0on bit in the ofs register is set to 1 and hardware reset. 4. power-on reset, voltage monitor 0 reset, or the lvd0on bit in the ofs register is set to 0 and hardware reset. 5. software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3. 6. this register is not implemented in the r8c/2j group. address register symbol after reset 0030h 0031h voltage detection register 1 (2) vca1 00001000b 0032h voltage detection register 2 (2) vca2 00h (3) 00100000b (4) 0033h 0034h 0035h 0036h voltage monitor 1 circuit control register (5) vw1c 00001010b 0037h voltage monitor 2 circuit control register (5) vw2c 00000010b 0038h voltage monitor 0 circuit control register (2) vw0c 1000x010b (3) 1100x011b (4) 0039h 003ah 003bh voltage detection circuit external input control register vcab 00h 003ch comparator mode register alcmr 00h 003dh voltage monitor circuit edge select register vcac 00h 003eh 003fh 0040h 0041h comparator 1 interrupt control register vcmp1ic xxxxx000b 0042h comparator 2 interrupt control register vcmp2ic xxxxx000b 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah timer re interrupt control register (6) treic xxxxx000b 004bh uart2 transmit interrupt control register (6) s2tic xxxxx000b 004ch uart2 receive interrupt control register (6) s2ric xxxxx000b 004dh key input interrupt control register kupic xxxxx000b 004eh 004fh 0050h compare 1 interrupt control register cmp1ic xxxxx000b 0051h uart0 transmit interrupt control register s0tic xxxxx000b 0052h uart0 receive interrupt control register s0ric xxxxx000b 0053h 0054h 0055h 0056h timer ra interrupt control register traic xxxxx000b 0057h 0058h timer rb interrupt control register trbic xxxxx000b 0059h int1 interrupt control register int1ic xx00x000b 005ah 005bh timer rf interrupt control register trfic xxxxx000b 005ch compare 0 interrupt control register cmp0ic xxxxx000b 005dh int0 interrupt control register int0ic xx00x000b 005eh 005fh capture interrupt control register capic xxxxx000b 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh 006ch 006dh 006eh 006fh
r8c/2h group, r8c/2j group 4. special function registers (sfrs) rev.0.10 jul 20, 2007 page 21 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change table 4.3 sfr information (3) (1) x: undefined note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008ah 008bh 008ch 008dh 008eh 008fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009ah 009bh 009ch 009dh 009eh 009fh 00a0h uart0 transmit/receive mode register u0mr 00h 00a1h uart0 bit rate register u0brg xxh 00a2h uart0 transmit buffer register u0tb xxh 00a3h xxh 00a4h uart0 transmit/receive control register 0 u0c0 00001000b 00a5h uart0 transmit/receive control register 1 u0c1 00000010b 00a6h uart0 receive buffer register u0rb xxh 00a7h xxh 00a8h 00a9h 00aah 00abh 00ach 00adh 00aeh 00afh
r8c/2h group, r8c/2j group 4. special function registers (sfrs) rev.0.10 jul 20, 2007 page 22 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change table 4.4 sfr information (4) (1) x: undefined note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 00b0h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h 00b9h 00bah 00bbh 00bch 00bdh 00beh 00bfh 00c0h 00c1h 00c2h 00c3h 00c4h 00c5h 00c6h 00c7h 00c8h 00c9h 00cah 00cbh 00cch 00cdh 00ceh 00cfh 00d0h 00d1h 00d2h 00d3h 00d4h 00d5h 00d6h 00d7h 00d8h 00d9h 00dah 00dbh 00dch 00ddh 00deh 00dfh 00e0h 00e1h port p1 register p1 00h 00e2h 00e3h port p1 direction register pd1 00h 00e4h 00e5h port p3 register p3 00h 00e6h 00e7h port p3 direction register pd3 00h 00e8h port p4 register p4 00h 00e9h 00eah port p4 direction register pd4 00h 00ebh 00ech port p6 register p6 00h 00edh 00eeh port p6 direction register pd6 00h 00efh
r8c/2h group, r8c/2j group 4. special function registers (sfrs) rev.0.10 jul 20, 2007 page 23 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change table 4.5 sfr information (5) (1) x: undefined note: 1. the blank regions are reserved. do not access locations in these regions 2. this register is not implemented in the r8c/2j group. address register symbol after reset 00f0h 00f1h 00f2h 00f3h 00f4h 00f5h 00f6h pin select register 2 pinsr2 00h 00f7h 00f8h port mode register pmr 00h 00f9h external input enable register inten 00h 00fah int input filter select register intf 00h 00fbh key input enable register kien 00h 00fch pull-up control register 0 pur0 00h 00fdh pull-up control register 1 pur1 00h 00feh 00ffh 0100h timer ra control register tracr 00h 0101h timer ra i/o control register traioc 00h 0102h timer ra mode register tramr 00h 0103h timer ra prescaler register trapre ffh 0104h timer ra register tra ffh 0105h 0106h lin control register lincr 00h 0107h lin status register linst 00h 0108h timer rb control register trbcr 00h 0109h timer rb one-shot control register trbocr 00h 010ah timer rb i/o control register trbioc 00h 010bh timer rb mode register trbmr 00h 010ch timer rb prescaler register trbpre ffh 010dh timer rb secondary register trbsc ffh 010eh timer rb primary register trbpr ffh 010fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h timer re second data register / counter data register (2) tresec 00h 0119h timer re minute data register / compare data register (2) tremin 00h 011ah timer re hour data register (2) trehr 00h 011bh timer re day of week data register (2) trewk 00h 011ch timer re control register 1 (2) trecr1 00h 011dh timer re control register 2 (2) trecr2 00h 011eh timer re clock source select register (2) trecsr 00001000b 011fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012ah 012bh 012ch 012dh 012eh 012fh
r8c/2h group, r8c/2j group 4. special function registers (sfrs) rev.0.10 jul 20, 2007 page 24 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change table 4.6 sfr information (6) (1) x: undefined note: 1. the blank regions are reserved. do not access locations in these regions. 2. this register is not implemented in the r8c/2j group. address register symbol after reset 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013ah 013bh 013ch 013dh 013eh 013fh 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014ah 014bh 014ch 014dh 014eh 014fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015ah 015bh 015ch 015dh 015eh 015fh 0160h uart2 transmit/receive mode register (2) u2mr 00h 0161h uart2 bit rate register (2) u2brg xxh 0162h uart2 transmit buffer register (2) u2tb xxh 0163h xxh 0164h uart2 transmit/receive control register 0 (2) u2c0 00001000b 0165h uart2 transmit/receive control register 1 (2) u2c1 00000010b 0166h uart2 receive buffer register (2) u2rb xxh 0167h xxh 0168h 0169h 016ah 016bh 016ch 016dh 016eh 016fh
r8c/2h group, r8c/2j group 4. special function registers (sfrs) rev.0.10 jul 20, 2007 page 25 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change table 4.7 sfr information (7) (1) x: undefined note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017ah 017bh 017ch 017dh 017eh 017fh 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018ah 018bh 018ch 018dh 018eh 018fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019ah 019bh 019ch 019dh 019eh 019fh 01a0h 01a1h 01a2h 01a3h 01a4h 01a5h 01a6h 01a7h 01a8h 01a9h 01aah 01abh 01ach 01adh 01aeh 01afh
r8c/2h group, r8c/2j group 4. special function registers (sfrs) rev.0.10 jul 20, 2007 page 26 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change table 4.8 sfr information (8) (1) x: undefined note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 01b0h 01b1h 01b2h 01b3h flash memory control register 4 fmr4 01000000b 01b4h 01b5h flash memory control register 1 fmr1 1000000xb 01b6h 01b7h flash memory control register 0 fmr0 00000001b 01b8h 01b9h 01bah 01bbh 01bch 01bdh 01beh 01bfh 01c0h 01c1h 01c2h 01c3h 01c4h 01c5h 01c6h 01c7h 01c8h 01c9h 01cah 01cbh 01cch 01cdh 01ceh 01cfh 01d0h 01d1h 01d2h 01d3h 01d4h 01d5h 01d6h 01d7h 01d8h 01d9h 01dah 01dbh 01dch 01ddh 01deh 01dfh 01e0h 01e1h 01e2h 01e3h 01e4h 01e5h 01e6h 01e7h 01e8h 01e9h 01eah 01ebh 01ech 01edh 01eeh 01efh
r8c/2h group, r8c/2j group 4. special function registers (sfrs) rev.0.10 jul 20, 2007 page 27 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change table 4.9 sfr information (9) (1) x: undefined note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 01f0h 01f1h 01f2h 01f3h 01f4h 01f5h 01f6h 01f7h 01f8h 01f9h 01fah 01fbh 01fch 01fdh 01feh 01ffh 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020ah 020bh 020ch 020dh 020eh 020fh 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021ah 021bh 021ch 021dh 021eh 021fh 0220h 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022ah 022bh 022ch 022dh 022eh 022fh
r8c/2h group, r8c/2j group 4. special function registers (sfrs) rev.0.10 jul 20, 2007 page 28 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change table 4.10 sfr information (10) (1) x: undefined note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023ah 023bh 023ch 023dh 023eh 023fh 0240h 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h 0249h 024ah 024bh 024ch 024dh 024eh 024fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025ah 025bh 025ch 025dh 025eh 025fh 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026ah 026bh 026ch 026dh 026eh 026fh
r8c/2h group, r8c/2j group 4. special function registers (sfrs) rev.0.10 jul 20, 2007 page 29 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change table 4.11 sfr information (11) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. after input capture mode. 3. after output compare mode. 4. this register is not implemented in the r8c/2j group. address register symbol after reset 0270h 0271h 0272h 0273h 0274h 0275h 0276h 0277h 0278h 0279h 027ah 027bh 027ch 027dh 027eh 027fh 0280h 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028ah 028bh 028ch 028dh 028eh 028fh 0290h timer rf register trf 00h 0291h 00h 0292h 0293h 0294h 0295h 0296h 0297h 0298h 0299h timer rf control register 2 (4) trfcr2 00h 029ah timer rf control register 0 trfcr0 00h 029bh timer rf control register 1 trfcr1 00h 029ch capture and compare 0 register trfm0 0000h (2) 029dh ffffh (3) 029eh compare 1 register trfm1 ffh 029fh ffh 02a0h 02a1h 02a2h 02a3h 02a4h 02a5h 02a6h 02a7h 02a8h 02a9h 02aah 02abh 02ach 02adh 02aeh 02afh
r8c/2h group, r8c/2j group 4. special function registers (sfrs) rev.0.10 jul 20, 2007 page 30 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change table 4.12 sfr information (12) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. the ofs register cannot be changed by a pr ogram. use a flash programmer to write to it. address register symbol after reset 02b0h 02b1h 02b2h 02b3h 02b4h 02b5h 02b6h 02b7h 02b8h 02b9h 02bah 02bbh 02bch 02bdh 02beh 02bfh 02c0h 02c1h 02c2h 02c3h 02c4h 02c5h 02c6h 02c7h 02c8h 02c9h 02cah 02cbh 02cch 02cdh 02ceh 02cfh 02d0h 02d1h 02d2h 02d3h 02d4h 02d5h 02d6h 02d7h 02d8h 02d9h 02dah 02dbh 02dch 02ddh 02deh 02dfh 02e0h 02efh 02f0h 02f1h 02f2h 02f3h 02f4h 02f5h 02f6h 02f7h 02f8h 02f9h 02fah 02fbh pin select register 4 pinsr4 00h 02fch 02fdh 02feh 02ffh timer rf output control register trfout 00h ffffh option function select register ofs (note 2)
r8c/2h group, r8c/2j group 5 . electrical characteristics rev.0.10 jul 20, 2007 page 31 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change 5. electrical characteristics 5.1 r8c/2h group notes: 1. v cc = 2.2 to 5.5 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. the typical values when average output current is 100 ms. figure 5.1 ports p1, p3, p4, and p6 timing measurement circuit table 5.1 absolute maximum ratings symbol parameter condition rated value unit v cc supply voltage ? 0.3 to 6.5 v v i input voltage ? 0.3 to v cc + 0.3 v v o output voltage ? 0.3 to v cc + 0.3 v p d power dissipation t opr = 25 c500mw t opr operating ambient temperature ? 20 to 85 (n version) / ? 40 to 85 (d version) c t stg storage temperature ? 65 to 150 c table 5.2 recommended operating conditions symbol parameter conditions standard unit min. typ. max. v cc supply voltage 2.2 ? 5.5 v v ss supply voltage ? 0 ? v v ih input ?h? voltage 0.8 v cc ? v cc v v il input ?l? voltage 0 ? 0.2 v cc v i oh(sum) peak sum output ?h? current sum of all pins i oh(peak) ??? 160 ma i oh(sum) average sum output ?h? current sum of all pins i oh(avg) ??? 80 ma i oh(peak) peak output ?h? current all pins ??? 10 ma i oh(avg) average output ?h? current all pins ??? 5ma i ol(sum) peak sum output ?l? currents sum of all pins i ol(peak) ?? 160 ma i ol(sum) average sum output ?l? currents sum of all pins i ol(avg) ?? 80 ma i ol(peak) peak output ?l? currents all pins ?? 10 ma i ol(avg) average output ?l? current all pins ?? 5ma f (xcin) xcin clock input oscillation frequency 2.2 v v cc 5.5 v 0 ? 70 khz ? system clock ocd2 = 0 xcln clock selected 2.2 v v cc 5.5 v 0 ? 70 khz ocd2 = 1 on-chip oscill ator clock selected hra01 = 0 low-speed on-chip oscillator selected ? 125 ? khz hra01 = 1 high-speed on-chip oscillator selected 2.7 v v cc 5.5 v ?? 8mhz hra01 = 1 high-speed on-chip oscillator selected 2.2 v v cc 5.5 v ?? 4mhz p1 p3 p4 p6 30pf
r8c/2h group, r8c/2j group 5 . electrical characteristics rev.0.10 jul 20, 2007 page 32 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change notes: 1. v cc = 2.7 to 5.5 v at t opr = 0 to 60 c, unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 4. in a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possib le is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 5. if an error occurs during block erase, attempt to execute t he clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 7. the data hold time includes time that the power supply is off or the clock is not supplied. figure 5.2 time delay until suspend table 5.3 flash memory (program rom) electrical characteristics symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) 100 (3) ?? times ? byte program time ? 50 400 s ? block erase time ? 0.4 9 s t d(sr-sus) time delay from suspend request until suspend ?? 97 + cpu clock 6 cycles s ? interval from erase start/restart until following suspend request 650 ?? s ? interval from program start/restart until following suspend request 0 ?? ns ? time from suspend until program/erase restart ?? 3 + cpu clock 4 cycles s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 2.2 ? 5.5 v ? program, erase temperature 0 ? 60 c ? data hold time (7) ambient temperature = 55 c20 ?? year fmr46 suspend request (maskable interrupt request) fixed time t d(sr-sus) clock-dependent time access restart
r8c/2h group, r8c/2j group 5 . electrical characteristics rev.0.10 jul 20, 2007 page 33 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change notes: 1. the measurement condition is v cc = 2.2 v to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version). 2. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca25 bit in the vca2 register to 0. notes: 1. the measurement condition is v cc = 2.2 v to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version). 2. time until the voltage monitor 1 interrupt request is generated after the voltage passes v det1 . 3. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca26 bit in the vca2 register to 0. 4. this parameter shows the voltage detection level when the power supply drops. the voltage detection level when the power supply rises is higher than the voltage detection level when the power supply drops by approximately 0.1 v. notes: 1. the measurement condition is v cc = 2.2 v to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version). 2. time until the voltage monitor 2 interrupt request is generated after the voltage passes v det2 . 3. necessary time until the voltage detection circuit operates after setting to 1 again af ter setting the vca27 bit in the vca2 register to 0. table 5.4 voltage detection 0 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det0 voltage detection level 2.2 2.3 2.4 v ? voltage detection circuit self power consumption vca25 = 1, v cc = 5.0 v ? 0.9 ? a t d(e-a) waiting time until voltage detection circuit operation starts (2) ?? 300 s vccmin mcu operating voltage minimum value 2.2 ?? v table 5.5 voltage detection 1 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det1 voltage detection level (4) 2.70 2.85 3.00 v ? voltage monitor 1 interrupt request generation time (2) ? 40 ? s ? voltage detection circuit self power consumption vca26 = 1, v cc = 5.0 v ? 0.6 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ?? 100 s table 5.6 voltage detection 2 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det2 voltage detection level 3.3 3.6 3.9 v ? voltage monitor 2 interrupt request generation time (2) ? 40 ? s ? voltage detection circuit self power consumption vca27 = 1, v cc = 5.0 v ? 0.6 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ?? 100 s
r8c/2h group, r8c/2j group 5 . electrical characteristics rev.0.10 jul 20, 2007 page 34 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change notes: 1. the measurement condition is t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. this condition (external power v cc rise gradient) does not apply if v cc 1.0 v. 3. to use the power-on reset function, enable voltage monitor 0 reset by setting the lvd0on bit in the ofs register to 0, the vw0c0 and vw0c6 bits in the vw0c register to 1 respectively, and the vca25 bit in the vca2 register to 1. 4. t w(por1) indicates the duration the external power v cc must be held below the effective voltage (v por1 ) to enable a power on reset. when turning on the power for the first time, maintain t w(por1) for 30 s or more if ? 20 c t opr 85 c, maintain t w(por1) for 3,000 s or more if ? 40 c t opr < ? 20 c. figure 5.3 reset circuit electrical characteristics table 5.7 power-on reset circuit, voltage monitor 0 reset electrical characteristics (3) symbol parameter condition standard unit min. typ. max. v por1 power-on reset valid voltage (4) ?? 0.1 v v por2 power-on reset or voltage monitor 0 reset valid voltage 0 ? v det0 v t rth external power v cc rise gradient (2) 20 ?? mv/msec notes: 1. when using the voltage monitor 0 digital filter, ensure that the voltage is within the mcu operation voltage range (2.2 v or above) during the sampling time. 2. the sampling clock can be selected. refer to 6. voltage detection circuit for details. 3. v det0 indicates the voltage detection level of the voltage detection 0 circuit. refer to 6. voltage detection circuit for details. v det0 (3) v por1 internal reset signal (?l? valid) t w(por1) sampling time (1, 2) v det0 (3) 1 f oco-s 32 1 f oco-s 32 v por2 2.2v external power v cc t rth t rth
r8c/2h group, r8c/2j group 5 . electrical characteristics rev.0.10 jul 20, 2007 page 35 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change note: 1. the measurement condition is t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. notes: 1. the measurement condition is t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. these standard values show when the hra1 register is set to the value before shipment and the hra2 register is set to 00h. note: 1. v cc = 2.2 to 5.5 v, t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. notes: 1. the measurement condition is v cc = 2.2 to 5.5 v and t opr = 25 c. 2. waiting time until the internal power s upply generation circuit stabilizes during power-on. 3. time until system clock supply starts after the interrupt is acknowledged to exit stop mode. table 5.8 comparator electrical characteristics symbol parameter condition standard unit min. typ. max. vref internal reference voltage v cc = 5.0 5.0 v, t opr = 25 c tbd 1.25 tbd v tbd 1.25 tbd v cvref external reference voltage input range ? tbd tbd v vcmp1, vcmp2 external comparison voltage input range ? tbd tbd v ? offset ? tbd tbd mv ? response time ? tbd tbd s ? comparator self power consumption ? tbd tbd a table 5.9 high-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco-f high-speed on-chip oscillator frequency temperature ? supply voltage dependence v cc = 4.75 v to 5.25 v 0 c t opr 60 c (2) 7.76 8 8.24 mhz v cc = 2.7 v to 5.5 v ? 20 c t opr 85 c (2) 7.68 8 8.32 mhz v cc = 2.7 v to 5.5 v ? 40 c t opr 85 c (2) 7.44 8 8.32 mhz v cc = 2.2 v to 5.5 v ? 20 c t opr 85 c (2) tbd 8 tbd mhz v cc = 2.2 v to 5.5 v ? 40 c t opr 85 c (2) tbd 8 tbd mhz table 5.10 low-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco-s low-speed on-chip oscillator frequency 30 125 250 khz ? oscillation st ability time ? 10 100 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? 15 ? a table 5.11 power supply circui t timing characteristics symbol parameter condition standard unit min. typ. max. t d(p-r) time for internal power supply stabilization during power-on (2) 1 ? tbd s t d(r-s) stop exit time (3) ?? tbd s
r8c/2h group, r8c/2j group 5 . electrical characteristics rev.0.10 jul 20, 2007 page 36 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change note: 1. v cc = 4.2 to 5.5 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. table 5.12 electrical characteristics (1) [v cc = 5 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage i oh = ? 5 ma v cc ? 2.0 ? v cc v i oh = ? 200 av cc ? 0.5 ? v cc v v ol output ?l? voltage i ol = 5 ma ?? 2.0 v i ol = 200 a ?? 0.45 v v t+- v t- hysteresis int0 , int1 , ki0 , ki1 , ki2 , ki3 , rxd0, rxd2, clk0, clk2 0.1 0.5 ? v reset 0.1 1.0 ? v i ih input ?h? current vi = 5 v, v cc = 5 v ?? 5.0 a i il input ?l? current vi = 0 v, v cc = 5 v ??? 5.0 a r pullup pull-up resistance vi = 0 v, v cc = 5 v 30 50 167 k ? r fxcin feedback resistance xcin ? 18 ? m ? v ram ram hold voltage during stop mode 2.0 ?? v
r8c/2h group, r8c/2j group 5 . electrical characteristics rev.0.10 jul 20, 2007 page 37 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change table 5.13 electrical characteristics (2) [vcc = 5 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 3.3 to 5.5 v) single-chip mode, output pins are open, other pins are v ss high-speed on-chip oscillator mode high-speed on-chip oscillator on = 8 mhz low-speed on-chip oscillator on = 125 khz no division ? tbd tbd ma high-speed on-chip oscillator on = 8 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? tbd ? ma low-speed on-chip oscillator mode high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? tbd tbd a low-speed clock mode high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) fmr47 = 1 ? tbd tbd a high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) program operation on ram flash memory off, fmstp = 1 ? tbd ? a wait mode high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd tbd a high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd tbd a high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (high drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd ? a high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd ? a stop mode xcin clock off, topr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? tbd tbd a xcin clock off, topr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? tbd ? a
r8c/2h group, r8c/2j group 5 . electrical characteristics rev.0.10 jul 20, 2007 page 38 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change timing requirements (unless otherwise specified: v cc = 5 v, v ss = 0 v at t opr = 25 c) [v cc = 5 v] figure 5.4 xcin input timing diagram when v cc = 5 v figure 5.5 traio input timing diagram when v cc = 5 v table 5.14 xcin input symbol parameter standard unit min. max. t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 5.15 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 100 ? ns t wh(traio) traio input ?h? width 40 ? ns t wl(traio) traio input ?l? width 40 ? ns xcin input t wh(xcin) t c(xcin) t wl(xcin) v cc = 5 v traio input v cc = 5 v t c(traio) t wl(traio) t wh(traio)
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 39 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change i = 0 or 2 figure 5.6 serial interface timing diagram when v cc = 5 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.7 external interrupt inti input timing diagram when v cc = 5 v table 5.16 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 200 ? ns t w(ckh) clki input ?h? width 100 ? ns t w(ckl) clki input ?l? width 100 ? ns t d(c-q) txdi output delay time ? 50 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 50 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.17 external interrupt inti (i = 0 or 1) input symbol parameter standard unit min. max. t w(inh) inti input ?h? width 250 (1) ? ns t w(inl) inti input ?l? width 250 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi i = 0 or 2 v cc = 5 v inti input t w(inl) t w(inh) i = 0 or 1 v cc = 5 v
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 40 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change note: 1. v cc =2.7 to 3.3 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. table 5.18 electrical characteristics (3) [v cc = 3 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage i oh = ? 1 ma v cc ? 0.5 ? v cc v v ol output ?l? voltage i ol = 1 ma ?? 0.5 v v t+- v t- hysteresis int0 , int1 , ki0 , ki1 , ki2 , ki3 , rxd0, rxd2, clk0, clk2 0.1 0.3 ? v reset 0.1 0.4 ? v i ih input ?h? current vi = 3 v, v cc = 3 v ?? 4.0 a i il input ?l? current vi = 0 v, v cc = 3 v ??? 4.0 a r pullup pull-up resistance vi = 0 v, v cc = 3 v 66 160 500 k ? r fxcin feedback resistance xcin ? 18 ? m ? v ram ram hold voltage during stop mode 1.8 ?? v
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 41 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change table 5.19 electrical characteristics (4) [vcc = 3 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 2.7 to 3.3 v) single-chip mode, output pins are open, other pins are v ss high-speed on-chip oscillator mode high-speed on-chip oscillator on = 8 mhz low-speed on-chip oscillator on = 125 khz no division ? tbd tbd ma high-speed on-chip oscillator on = 8 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? tbd ? ma low-speed on-chip oscillator mode high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? tbd tbd a low-speed clock mode high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) fmr47 = 1 ? tbd tbd a high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) program operation on ram flash memory off, fmstp = 1 ? tbd ? a wait mode high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd tbd a high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd tbd a high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (high drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd ? a high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd ? a stop mode xcin clock off , t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? tbd tbd a xcin clock off , t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? tbd ? a
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 42 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change timing requirements (unless otherwise specified: v cc = 3 v, v ss = 0 v at t opr = 25 c) [v cc = 3 v] figure 5.8 xcin input timing diagram when v cc = 3 v figure 5.9 traio input timing diagram when v cc = 3 v table 5.20 xcin input symbol parameter standard unit min. max. t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 5.21 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 300 ? ns t wh(traio) traio input ?h? width 120 ? ns t wl(traio) traio input ?l? width 120 ? ns xcin input t wh(xcin) t c(xcin) t wl(xcin) v cc = 3 v traio input v cc = 3 v t c(traio) t wl(traio) t wh(traio)
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 43 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change i = 0 or 2 figure 5.10 serial interface timing diagram when v cc = 3 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.11 external interrupt inti input timing diagram when v cc = 3 v table 5.22 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 300 ? ns t w(ckh) clki input ?h? width 150 ? ns t w(ckl) clki input ?l? width 150 ? ns t d(c-q) txdi output delay time ? 80 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 70 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.23 external interrupt inti (i = 0 or 1) input symbol parameter standard unit min. max. t w(inh) inti input ?h? width 380 (1) ? ns t w(inl) inti input ?l? width 380 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 3 v i = 0 or 2 inti input t w(inl) t w(inh) v cc = 3 v i = 0 or 1
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 44 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change note: 1. v cc = 2.2 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. table 5.24 electrical characteristics (5) [v cc = 2.2 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage i oh = ? 1 ma v cc ? 0.5 ? v cc v v ol output ?l? voltage i ol = 1 ma ?? 0.5 v v t+- v t- hysteresis int0 , int1 , ki0 , ki1 , ki2 , ki3 , rxd0, rxd2, clk0, clk2 0.05 0.3 ? v reset 0.05 0.15 ? v i ih input ?h? current vi = 2.2 v ?? 4.0 a i il input ?l? current vi = 0 v ??? 4.0 a r pullup pull-up resistance vi = 0 v 100 200 600 k ? r fxcin feedback resistance xcin ? 35 ? m ? v ram ram hold voltage during stop mode 1.8 ?? v
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 45 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change table 5.25 electrical characteristics (6) [vcc = 2.2 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 2.2 to 2.7 v) single-chip mode, output pins are open, other pins are v ss high-speed on-chip oscillator mode high-speed on-chip oscillator on = 4 mhz low-speed on-chip oscillator on = 125 khz no division ? tbd ? ma high-speed on-chip oscillator on = 4 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? tbd ? ma low-speed on-chip oscillator mode high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? tbd tbd a low-speed clock mode high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) fmr47 = 1 ? tbd tbd a high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) program operation on ram flash memory off, fmstp = 1 ? tbd ? a wait mode high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd tbd a high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd tbd a high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (high drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd ? a high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd ? a stop mode xcin clock off , t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? tbd tbd a xcin clock off , t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? tbd ? a
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 46 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change timing requirements (unless otherwise specified: v cc = 2.2 v, v ss = 0 v at t opr = 25 c) [v cc = 2.2 v] figure 5.12 xcin input timing diagram when v cc = 2.2 v figure 5.13 traio input timing diagram when v cc = 2.2 v table 5.26 xcin input symbol parameter standard unit min. max. t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 5.27 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 500 ? ns t wh(traio) traio input ?h? width 200 ? ns t wl(traio) traio input ?l? width 200 ? ns xcin input t wh(xcin) t c(xcin) t wl(xcin) v cc = 2.2 v traio input t c(traio) t wl(traio) t wh(traio) v cc = 2.2 v
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 47 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change i = 0 or 2 figure 5.14 serial interface timing diagram when v cc = 2.2 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.15 external interrupt inti input timing diagram when v cc = 2.2 v table 5.28 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 800 ? ns t w(ckh) clki input ?h? width 400 ? ns t w(ckl) clki input ?l? width 400 ? ns t d(c-q) txdi output delay time ? 200 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 150 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.29 external interrupt inti (i = 0 or 1) input symbol parameter standard unit min. max. t w(inh) inti input ?h? width 1000 (1) ? ns t w(inl) inti input ?l? width 1000 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 2.2 v i = 0 or 2 inti input t w(inl) t w(inh) v cc = 2.2 v i = 0 or 1
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 48 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change 5.2 r8c/2j group notes: 1. v cc = 2.2 to 5.5 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. the typical values when average output current is 100 ms. figure 5.16 ports p1, p3, p4, and p6 timing measurement circuit table 5.30 absolute maximum ratings symbol parameter condition rated value unit v cc supply voltage ? 0.3 to 6.5 v v i input voltage ? 0.3 to v cc + 0.3 v v o output voltage ? 0.3 to v cc + 0.3 v p d power dissipation t opr = 25 c500mw t opr operating ambient temperature ? 20 to 85 (n version) / ? 40 to 85 (d version) c t stg storage temperature ? 65 to 150 c table 5.31 recommended operating conditions symbol parameter conditions standard unit min. typ. max. v cc supply voltage 2.2 ? 5.5 v v ss supply voltage ? 0 ? v v ih input ?h? voltage 0.8 v cc ? v cc v v il input ?l? voltage 0 ? 0.2 v cc v i oh(sum) peak sum output ?h? current sum of all pins i oh(peak) ??? 160 ma i oh(sum) average sum output ?h? current sum of all pins i oh(avg) ??? 80 ma i oh(peak) peak output ?h? current all pins ??? 10 ma i oh(avg) average output ?h? current all pins ??? 5ma i ol(sum) peak sum output ?l? currents sum of all pins i ol(peak) ?? 160 ma i ol(sum) average sum output ?l? currents sum of all pins i ol(avg) ?? 80 ma i ol(peak) peak output ?l? currents all pins ?? 10 ma i ol(avg) average output ?l? current all pins ?? 5ma ? system clock hra01 = 0 low-speed on-chip oscillator selected ? 125 ? khz hra01 = 1 high-speed on-chip oscillator selected 2.7 v v cc 5.5 v ?? 8mhz hra01 = 1 high-speed on-chip oscillator selected 2.2 v v cc 5.5 v ?? 4mhz p1 p3 p4 p6 30pf
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 49 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change notes: 1. v cc = 2.7 to 5.5 v at t opr = 0 to 60 c, unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 4. in a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possib le is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 5. if an error occurs during block erase, attempt to execute t he clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 7. the data hold time includes time that the power supply is off or the clock is not supplied. figure 5.17 time delay until suspend table 5.32 flash memory (program rom) electrical characteristics symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) 100 (3) ?? times ? byte program time ? 50 400 s ? block erase time ? 0.4 9 s t d(sr-sus) time delay from suspend request until suspend ?? 97 + cpu clock 6 cycles s ? interval from erase start/restart until following suspend request 650 ?? s ? interval from program start/restart until following suspend request 0 ?? ns ? time from suspend until program/erase restart ?? 3 + cpu clock 4 cycles s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 2.2 ? 5.5 v ? program, erase temperature 0 ? 60 c ? data hold time (7) ambient temperature = 55 c20 ?? year fmr46 suspend request (maskable interrupt request) fixed time t d(sr-sus) clock-dependent time access restart
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 50 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change notes: 1. the measurement condition is v cc = 2.2 v to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version). 2. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca25 bit in the vca2 register to 0. notes: 1. the measurement condition is v cc = 2.2 v to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version). 2. time until the voltage monitor 1 interrupt request is generated after the voltage passes v det1 . 3. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca26 bit in the vca2 register to 0. 4. this parameter shows the voltage detection level when the power supply drops. the voltage detection level when the power supply rises is higher than the voltage detection level when the power supply drops by approximately 0.1 v. notes: 1. the measurement condition is v cc = 2.2 v to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version). 2. time until the voltage monitor 2 interrupt request is generated after the voltage passes v det2 . 3. necessary time until the voltage detection circuit operates after setting to 1 again af ter setting the vca27 bit in the vca2 register to 0. table 5.33 voltage detection 0 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det0 voltage detection level 2.2 2.3 2.4 v ? voltage detection circuit self power consumption vca25 = 1, v cc = 5.0 v ? 0.9 ? a t d(e-a) waiting time until voltage detection circuit operation starts (2) ?? 300 s vccmin mcu operating voltage minimum value 2.2 ?? v table 5.34 voltage detection 1 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det1 voltage detection level (4) 2.70 2.85 3.00 v ? voltage monitor 1 interrupt request generation time (2) ? 40 ? s ? voltage detection circuit self power consumption vca26 = 1, v cc = 5.0 v ? 0.6 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ?? 100 s table 5.35 voltage detection 2 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det2 voltage detection level 3.3 3.6 3.9 v ? voltage monitor 2 interrupt request generation time (2) ? 40 ? s ? voltage detection circuit self power consumption vca27 = 1, v cc = 5.0 v ? 0.6 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ?? 100 s
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 51 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change notes: 1. the measurement condition is t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. this condition (external power v cc rise gradient) does not apply if v cc 1.0 v. 3. to use the power-on reset function, enable voltage monitor 0 reset by setting the lvd0on bit in the ofs register to 0, the vw0c0 and vw0c6 bits in the vw0c register to 1 respectively, and the vca25 bit in the vca2 register to 1. 4. t w(por1) indicates the duration the external power v cc must be held below the effective voltage (v por1 ) to enable a power on reset. when turning on the power for the first time, maintain t w(por1) for 30 s or more if ? 20 c t opr 85 c, maintain t w(por1) for 3,000 s or more if ? 40 c t opr < ? 20 c. figure 5.18 reset circuit el ectrical characteristics table 5.36 power-on reset circuit, voltage monitor 0 reset electrical characteristics (3) symbol parameter condition standard unit min. typ. max. v por1 power-on reset valid voltage (4) ?? 0.1 v v por2 power-on reset or voltage monitor 0 reset valid voltage 0 ? v det0 v t rth external power v cc rise gradient (2) 20 ?? mv/msec notes: 1. when using the voltage monitor 0 digital filter, ensure that the voltage is within the mcu operation voltage range (2.2 v or above) during the sampling time. 2. the sampling clock can be selected. refer to 6. voltage detection circuit for details. 3. v det0 indicates the voltage detection level of the voltage detection 0 circuit. refer to 6. voltage detection circuit for details. v det0 (3) v por1 internal reset signal (?l? valid) t w(por1) sampling time (1, 2) v det0 (3) 1 f oco-s 32 1 f oco-s 32 v por2 2.2v external power v cc t rth t rth
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 52 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change note: 1. the measurement condition is t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. notes: 1. the measurement condition is t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. these standard values show when the hra1 register is set to the value before shipment and the hra2 register is set to 00h. note: 1. v cc = 2.2 to 5.5 v, t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. notes: 1. the measurement condition is v cc = 2.2 to 5.5 v and t opr = 25 c. 2. waiting time until the internal power s upply generation circuit stabilizes during power-on. 3. time until system clock supply starts after the interrupt is acknowledged to exit stop mode. table 5.37 comparator electrical characteristics symbol parameter condition standard unit min. typ. max. vref internal reference voltage v cc = 5.0 5.0 v, t opr = 25 c tbd 1.25 tbd v tbd 1.25 tbd v cvref external reference voltage input range ? tbd tbd v vcmp1, vcmp2 external comparison voltage input range ? tbd tbd v ? offset ? tbd tbd mv ? response time ? tbd tbd s ? comparator self power consumption ? tbd tbd a table 5.38 high-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco-f high-speed on-chip oscillator frequency temperature ? supply voltage dependence v cc = 4.75 v to 5.25 v 0 c t opr 60 c (2) 7.76 8 8.24 mhz v cc = 2.7 v to 5.5 v ? 20 c t opr 85 c (2) 7.68 8 8.32 mhz v cc = 2.7 v to 5.5 v ? 40 c t opr 85 c (2) 7.44 8 8.32 mhz v cc = 2.2 v to 5.5 v ? 20 c t opr 85 c (2) tbd 8 tbd mhz v cc = 2.2 v to 5.5 v ? 40 c t opr 85 c (2) tbd 8 tbd mhz table 5.39 low-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco-s low-speed on-chip oscillator frequency 30 125 250 khz ? oscillation st ability time ? 10 100 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? 15 ? a table 5.40 power supply circuit timing characteristics symbol parameter condition standard unit min. typ. max. t d(p-r) time for internal power supply stabilization during power-on (2) 1 ? tbd s t d(r-s) stop exit time (3) ?? tbd s
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 53 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change note: 1. v cc = 4.2 to 5.5 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. table 5.41 electrical characteristics (1) [v cc = 5 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage i oh = ? 5 ma v cc ? 2.0 ? v cc v i oh = ? 200 av cc ? 0.5 ? v cc v v ol output ?l? voltage i ol = 5 ma ?? 2.0 v i ol = 200 a ?? 0.45 v v t+- v t- hysteresis int0 , int1 , ki0 , ki1 , ki2 , ki3 , rxd0, clk0 0.1 0.5 ? v reset 0.1 1.0 ? v i ih input ?h? current vi = 5 v, v cc = 5 v ?? 5.0 a i il input ?l? current vi = 0 v, v cc = 5 v ??? 5.0 a r pullup pull-up resistance vi = 0 v, v cc = 5 v 30 50 167 k ? v ram ram hold voltage during stop mode 2.0 ?? v
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 54 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change table 5.42 electrical characteristics (2) [vcc = 5 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 3.3 to 5.5 v) single-chip mode, output pins are open, other pins are v ss high-speed on-chip oscillator mode high-speed on-chip oscillator on = 8 mhz low-speed on-chip oscillator on = 125 khz no division ? tbd tbd ma high-speed on-chip oscillator on = 8 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? tbd ? ma low-speed on-chip oscillator mode high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? tbd tbd a wait mode high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd tbd a high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd tbd a high-speed on-chip oscillator off low-speed on-chip oscillator off while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd ? a high-speed on-chip oscillator off low-speed on-chip oscillator off while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd ? a stop mode topr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? tbd tbd a topr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? tbd ? a
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 55 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change timing requirements (unless otherwise specified: v cc = 5 v, v ss = 0 v at t opr = 25 c) [v cc = 5 v] figure 5.19 traio input timing diagram when v cc = 5 v table 5.43 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 100 ? ns t wh(traio) traio input ?h? width 40 ? ns t wl(traio) traio input ?l? width 40 ? ns traio input v cc = 5 v t c(traio) t wl(traio) t wh(traio)
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 56 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change figure 5.20 serial interface timing diagram when v cc = 5 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.21 external interrupt inti input timing diagram when v cc = 5 v table 5.44 serial interface symbol parameter standard unit min. max. t c(ck) clk0 input cycle time 200 ? ns t w(ckh) clk0 input ?h? width 100 ? ns t w(ckl) clk0 input ?l? width 100 ? ns t d(c-q) txd0 output delay time ? 50 ns t h(c-q) txd0 hold time 0 ? ns t su(d-c) rxd0 input setup time 50 ? ns t h(c-d) rxd0 input hold time 90 ? ns table 5.45 external interrupt inti (i = 0 or 1) input symbol parameter standard unit min. max. t w(inh) inti input ?h? width 250 (1) ? ns t w(inl) inti input ?l? width 250 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clk0 txd0 rxd0 v cc = 5 v inti input t w(inl) t w(inh) i = 0 or 1 v cc = 5 v
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 57 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change note: 1. v cc =2.7 to 3.3 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. table 5.46 electrical characteristics (3) [v cc = 3 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage i oh = ? 1 ma v cc ? 0.5 ? v cc v v ol output ?l? voltage i ol = 1 ma ?? 0.5 v v t+- v t- hysteresis int0 , int1 , ki0 , ki1 , ki2 , ki3 , rxd0, clk0 0.1 0.3 ? v reset 0.1 0.4 ? v i ih input ?h? current vi = 3 v, v cc = 3 v ?? 4.0 a i il input ?l? current vi = 0 v, v cc = 3 v ??? 4.0 a r pullup pull-up resistance vi = 0 v, v cc = 3 v 66 160 500 k ? v ram ram hold voltage during stop mode 1.8 ?? v
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 58 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change table 5.47 electrical characteristics (4) [vcc = 3 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 2.7 to 3.3 v) single-chip mode, output pins are open, other pins are v ss high-speed on-chip oscillator mode high-speed on-chip oscillator on = 8 mhz low-speed on-chip oscillator on = 125 khz no division ? tbd tbd ma high-speed on-chip oscillator on = 8 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? tbd ? ma low-speed on-chip oscillator mode high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? tbd tbd a wait mode high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd tbd a high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd tbd a high-speed on-chip oscillator off low-speed on-chip oscillator off while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd ? a high-speed on-chip oscillator off low-speed on-chip oscillator off while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd ? a stop mode t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? tbd tbd a t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? tbd ? a
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 59 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change timing requirements (unless otherwise specified: v cc = 3 v, v ss = 0 v at t opr = 25 c) [v cc = 3 v] figure 5.22 traio input timing diagram when v cc = 3 v table 5.48 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 300 ? ns t wh(traio) traio input ?h? width 120 ? ns t wl(traio) traio input ?l? width 120 ? ns traio input v cc = 3 v t c(traio) t wl(traio) t wh(traio)
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 60 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change figure 5.23 serial interface timing diagram when v cc = 3 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.24 external interrupt inti input timing diagram when v cc = 3 v table 5.49 serial interface symbol parameter standard unit min. max. t c(ck) clk0 input cycle time 300 ? ns t w(ckh) clk0 input ?h? width 150 ? ns t w(ckl) clk0 input ?l? width 150 ? ns t d(c-q) txd0 output delay time ? 80 ns t h(c-q) txd0 hold time 0 ? ns t su(d-c) rxd0 input setup time 70 ? ns t h(c-d) rxd0 input hold time 90 ? ns table 5.50 external interrupt inti (i = 0 or 1) input symbol parameter standard unit min. max. t w(inh) inti input ?h? width 380 (1) ? ns t w(inl) inti input ?l? width 380 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clk0 txd0 rxd0 v cc = 3 v inti input t w(inl) t w(inh) v cc = 3 v i = 0 or 1
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 61 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change note: 1. v cc = 2.2 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. table 5.51 electrical characteristics (5) [v cc = 2.2 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage i oh = ? 1 ma v cc ? 0.5 ? v cc v v ol output ?l? voltage i ol = 1 ma ?? 0.5 v v t+- v t- hysteresis int0 , int1 , ki0 , ki1 , ki2 , ki3 , rxd0, clk0 0.05 0.3 ? v reset 0.05 0.15 ? v i ih input ?h? current vi = 2.2 v ?? 4.0 a i il input ?l? current vi = 0 v ??? 4.0 a r pullup pull-up resistance vi = 0 v 100 200 600 k ? r fxcin feedback resistance xcin ? 35 ? m ? v ram ram hold voltage during stop mode 1.8 ?? v
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 62 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change table 5.52 electrical characteristics (6) [vcc = 2.2 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 2.2 to 2.7 v) single-chip mode, output pins are open, other pins are v ss high-speed on-chip oscillator mode high-speed on-chip oscillator on = 4 mhz low-speed on-chip oscillator on = 125 khz no division ? tbd ? ma high-speed on-chip oscillator on = 4 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? tbd ? ma low-speed on-chip oscillator mode high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? tbd tbd a wait mode high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd tbd a high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd tbd a high-speed on-chip oscillator off low-speed on-chip oscillator off while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd ? a high-speed on-chip oscillator off low-speed on-chip oscillator off while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? tbd ? a stop mode t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? tbd tbd a t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? tbd ? a
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 63 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change timing requirements (unless otherwise specified: v cc = 2.2 v, v ss = 0 v at t opr = 25 c) [v cc = 2.2 v] figure 5.25 traio input timing diagram when v cc = 2.2 v table 5.53 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 500 ? ns t wh(traio) traio input ?h? width 200 ? ns t wl(traio) traio input ?l? width 200 ? ns traio input t c(traio) t wl(traio) t wh(traio) v cc = 2.2 v
r8c/2h group, r8c/2j group 5. electrical characteristics rev.0.10 jul 20, 2007 page 64 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change figure 5.26 serial interface timing diagram when v cc = 2.2 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.27 external interrupt inti input timing diagram when v cc = 2.2 v table 5.54 serial interface symbol parameter standard unit min. max. t c(ck) clk0 input cycle time 800 ? ns t w(ckh) clk0 input ?h? width 400 ? ns t w(ckl) clk0 input ?l? width 400 ? ns t d(c-q) txd0 output delay time ? 200 ns t h(c-q) txd0 hold time 0 ? ns t su(d-c) rxd0 input setup time 150 ? ns t h(c-d) rxd0 input hold time 90 ? ns table 5.55 external interrupt inti (i = 0 or 1) input symbol parameter standard unit min. max. t w(inh) inti input ?h? width 1000 (1) ? ns t w(inl) inti input ?l? width 1000 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clk0 txd0 rxd0 v cc = 2.2 v inti input t w(inl) t w(inh) v cc = 2.2 v i = 0 or 1
r8c/2h group, r8c/2j group package dimensions rev.0.10 jul 20, 2007 page 65 of 65 rej03b0217-0010 under development preliminary specification specications in this manual are tentative and subject to change package dimensions diagrams showing the latest package dimensions and mounti ng information are available in the ?packages? section of the renesas technology website. y index mark 1 10 11 20 f * 1 * 3 * 2 c b p e a d e h e include trim offset. dimension " * 3" does not note) do not include mold flash. dimensions " * 1" and " * 2" 1. 2. detail f a 1 a 2 l 0.32 0.22 0.17 b p previous code jeita package code renesas code plsp0020jb-a 20p2f-a mass[typ.] 0.1g p-lssop20-4.4x6.5-0.65 0.2 0.15 0.13 max nom min dimension in millimeters symbol reference 6.6 6.5 6.4 d 4.5 4.4 4.3 e 1.15 a 2 6.6 6.4 6.2 1.45 a 0.2 0.1 0 0.7 0.5 0.3 l 10 0 c 0.65 e 0.10 y h e a 1 0.53 0.77
c - 1 revision history r8c/2h group, r8c/ 2j group datasheet rev. date description page summary 0.01 jun 18, 2007 ?
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